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Architectural Design
1. Responsible for the overall scheme design of the FPGA, including module division, clock planning, resource estimation and chip selection.
2. Participate in the hardware schematic review and output optimization suggestions from the perspectives of pin assignment, signal integrity, clock scheme, etc.
3. Formulate development specifications and validation standards, and establish a reusable IP module library.
Core Development
1. Responsible for RTL/Block Design implementation and debugging of sensor interfaces (MIPI CSI-2/D-PHY, SLVS-EC, LVDS) and high-speed video output interfaces (SDI, HDMI 2.0+, Camera Link).
2. Responsible for controller configuration and bandwidth optimization of high-speed storage interfaces (DDR3/4/5, NVMe/PCIe).
3. Responsible for the implementation of high-precision synchronization mechanisms such as synchronization systems (Genlock, TC, PTP).
4. Collaborate with the algorithm team to convert ISP algorithms (noise reduction, HDR synthesis, color correction, etc.) and image and video codec algorithms into FPGA hardware implementations.
Verification & Commissioning
1. Build an automated simulation and verification platform to ensure the correctness of the module function.
2. Responsible for timing constraint design and convergence optimization, resource and power consumption optimization.
3. Use oscilloscopes, logic analyzers, ILAs and other tools to complete board-level debugging and collaboratively locate system-level problems.
Foundation Threshold
1. Undergraduate and above, electronic engineering/microelectronics/Communication/automation and other related majors, more than 5 years of FPGA development experience, fully involved in the mass production development of at least 2 imaging/video products.
Core Skills
1. Proficient in Verilog/SystemVerilog;
2. Proficient in Xilinx (UltraScale +/Versal/Zynq) or Intel (Agilex) series FPGAs, proficient in Vivado/Quartus and supporting simulation tools.
3. Experience in high-speed interface development, proficient in at least two types: sensor interface (MIPI CSI-2), video interface (SDI/HDMI), storage interface (DDR/PCIe), familiar with NOC debugging is preferred.
4. Master the timing constraints, cross-clock domain processing, signal integrity analysis, and can independently complete the timing convergence of complex designs.
5. Can read schematic diagrams independently, and is proficient in board-level debugging using oscilloscopes, logic analyzers and other tools.
6. Familiar with Tcl/Python scripts, able to write automated simulation and build processes.
Industry Plus (camera/image orientation first)
1. Experience in FPGA development for cameras/camcorders/broadcast cameras, etc.
2. Have experience in FPGA implementation of ISP algorithms, or have experience in IP core integration and customization such as Vitis Video.
3. Familiar with hardware acceleration implementation of professional coding standards (ProRes, DNxHD, raw coding, etc.).
4.Familiar with Genlock, SMPTE time code, PTP and other multi-device synchronization technologies.
5. Experience in hardware implementation of aces color workflow and HDR production process.
6. Familiar with SMPTE/EBU and other industry standards, with product certification experience.
General Plus
1. Experience in building SoC systems (Zynq PS + PL collaborative design), familiar with arm and FPGA data interaction schemes.
2. Experience with AI inference acceleration and deep learning model FPGA deployment.
3. Successful cases of FPGA system restructuring and platform design, with clear architectural thinking.